Synopsys Accelerates Multi-Die Designs with Industry’s First Complete HBM3 IP and Verification Solutions

Synopsys Accelerates Multi-Die Designs with Industry's First Complete HBM3 IP and Verification Solutions-01

Synopsys, Inc. today announced the industry’s first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys’ DesignWare® HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys’ interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.

The Synopsys verification solution, including Verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu® emulation, and HAPS® prototyping system, accelerates verification from HBM3 IP to SoCs. To accelerate development of HBM3 system designs, Synopsys’ 3DIC Compiler multi-die design platform provides a fully integrated architectural exploration, implementation and system-level analysis solution.

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Synopsys’ DesignWare HBM3 Controller IP supports a variety of HBM3-based systems with flexible configuration options. The controller minimizes latency and optimizes data integrity with advanced RAS features that include error correction code, refresh management and parity.

The DesignWare HBM3 PHY IP in 5-nm process, available as pre-hardened or customer configurable PHY, operates at up to 7200 Mbps per pin, significantly improves power efficiency and supports up to four active operating states enabling dynamic frequency scaling. The DesignWare HBM3 PHY utilizes an optimized micro bump array to help minimize area. The support for interposer trace lengths gives designers more flexibility in the PHY placement without impacting performance.

Synopsys Verification IP for HBM3 uses next-generation native SystemVerilog Universal Verification Methodology architecture to ease integration of existing verification environments and run a greater number of tests, accelerating time to first test. The off-the-shelf HBM3 memory models for ZeBu emulation and HAPS prototyping system enable RTL and software verification for higher levels of performance.

“Synopsys continues to address the design and verification requirements of data-intensive SoCs with high-quality memory interface IP and verification solutions for the most advanced protocols like HBM3, DDR5 and LPDDR5,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “The complete HBM3 IP and verification solutions enable designers to meet increasing bandwidth, latency and power requirements while accelerating verification closure, all from a single, trusted provider.”

Synopsys’ broad DesignWare IP portfolio includes logic libraries, embedded memories, PVT sensors, embedded test, analog IP, interface IP, security IP, embedded processors and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP prototyping kits, IP software development kits and IP subsystems. Our extensive investment in IP quality and comprehensive technical support enable designers to reduce integration risk and accelerate time-to-market. For more information,

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