Synopsys, Inc. announced that SiFive, Inc. has selected Synopsys Fusion Design Platform™ and Verification Continuum® platform to enable the rapid cloud-based design of next-generation customer silicon products. Building on SiFive’s successful track record utilizing Synopsys’ design and verification solutions for the development of its IP cores and SoC templates, SiFive will incorporate these solutions in its cloud-based methodology to create customized SoCs for select lead access customers to achieve best quality-of-results (QoR) and time-to-results (TTR) for its next-generation system-on-chip (SoC) designs.
“SiFive’s mission is to simplify idea-to-silicon, enabling designers with a new way of building custom SoCs,” said Yunsup Lee, CTO of SiFive. “As the leading provider of design and verification solutions, Synopsys delivers the trusted path to create domain-specific SoCs optimized to meet product requirements in markets such as automotive, industrial and consumer IoT. We are collaborating closely with Synopsys to enable the cloud-based design of SiFive customers’ next-generation SoCs.”
During this initial phase of the collaboration, SiFive plans to use Synopsys’ Fusion Design Platform and Verification Continuum platform in the cloud to create custom SoCs for SiFive customers.
“Azure is working closely with Synopsys to continue pushing scalability of EDA tools to leverage the cloud, and with SiFive to enable configurable, scalable SoC design with SiFive Core Designer, which further validates the readiness of cloud for silicon design,” said Mujtaba Hamid, head of product management, Silicon, Electronics and Gaming at Microsoft Azure. “The collaboration between Azure, SiFive, and Synopsys will continue to lower the barrier to entry for new customers and continue to improve productivity of doing custom SoC design.”
The Fusion Design Platform incorporates many Synopsys industry-leading solutions, enabling:
- 7nm and below implementation in Synopsys’ Fusion Compiler™ RTL-to-GDSII product, Design Compiler® graphical synthesis tool, and IC Compiler™ II place-and-route system
- Higher performance with automatic density control and timing-driven placement
- Lower power with full-flow concurrent clock and datapath (CCD) optimization
- Signoff closure with PrimeTime® PBA-based ECO with power recovery and exhaustive PBA along with StarRC™ simultaneous multi-corner extraction
- Early, accelerated design optimization for power integrity and reliability with the RedHawk™ Analysis Fusion signoff-driven flow within IC Compiler II
The Verification Continuum platform includes:
- Industry-leading VCS® with native low power simulation for mixed-language RTL and gate-level with the smallest memory footprint
- Industry de-facto standard Verdi® advanced debug solution
- VC Verification IP for emerging titles, including PCIe Gen5, CXL, DDR5, LPDDR5, and USB4
- SpyGlass® for RTL signoff and VC LP™ for static low power signoff
- VC Formal™ verification solution for faster formal coverage closure