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Achronix Adopts Movellus Maestro Clock Network for Its Speedster7t FPGAs

By ET Bureau - March 24, 2021 2 Mins Read

Achronix Adopts Movellus Maestro Clock Network for Its Speedster7t FPGAs

Movellus, Inc. today announced that Achronix, a leader in high-performance FPGAs and embedded FPGA (eFPGA) IP, has adopted Movellus’ Maestro intelligent clocking solution for its Speedster®7t FPGAs.

Speedster®7t FPGAs are used in high-performance communications, artificial intelligence, machine learning, automotive driver assistance, compute acceleration, industrial and military applications.

Achronix offerings include discrete high-performance and high-density FPGAs with hardwired system-level blocks, embedded FPGA IP, PCI Express form factor datacenter and HPC hardware accelerator cards, and best-in-class EDA software supporting all Achronix products.

The latest Speedster®7t high-density and high-performance FPGA family is optimized to meet the growing demands of AI/ML and high-bandwidth data acceleration applications.

Speedster7t devices offer a unique 2D NoC that allows for ASIC-level performance data transfers between the FPGA fabric and the high speed interfaces including GDDR6 and DDR4/5 memory interfaces, 400G Ethernet and PCI Express Gen5 ports.

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“We were impressed by the increased performance and power-efficiency our system design team was able to achieve using the TrueDigital™ Module within the Maestro intelligent clock network platform,” said Chris Pelosi, VP of Hardware Engineering at Achronix. “We were also pleasantly surprised by how quickly and easily we were able to adopt Movellus’ all-digital clocking solution which fit in seamlessly within our existing digital methodology.

“Achronix’s leadership in FPGA and eFPGA IP for data acceleration is unrivaled,” said Mo Faisal, President and CEO of Movellus. “We are excited to be part of an innovative solution that is enabling the rapid advancement of exciting markets such as AI, Cloud, 5G, ADAS, and autonomous systems.”

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